The present invention relates to data processing devices requiring high reliability such as disk arrays and server devices whose object is to hold data, and relates in particular to a data processing device and memory correction method for the data processing device for correcting the memory using an error check code and improving the data reliability.
FIG. 14 is a descriptive view of memory correction in the related art. FIG. 14 shows the data path used when writing data from host 100 onto memory module 110, and shows the data path when transferring read data from memory module 110 to host 100.
When the host 100 writes data into memory module 110 via host bus 102, error checking code (ECC) generator circuit 104 generates a 16-bit ECC code for 128-bit write data 103, and after passing through write buffer 106 and write-back selector 107, the data is finally written into memory module 110 in a state where ECC code 109 is attached to write data 108.
When host 100 makes a request, read data 111 and read ECC code 112 belonging to data 111 are read out from memory module 110. ECC check circuit 113 makes an error check. If an error is detected, then read data 111 and read ECC code 112 are input to syndrome generator circuit 114, and a syndrome is generated to show the error location (i.e., the location needing correction). Modifier circuit 115 performs data correction on read data 111, so that normal data is restored.
In high reliability server devices, write ECC code 109 stored in memory module 110 in FIG. 14, at this time utilizes an S4EC-D4ED code which is 16 bits of write data 108 versus the 128-bit write data 108, and corrects single blocks of 4 bits each using a 1-block correction—2-block error detection function. Besides this code, an SEC-DED code may be utilized for example, for 1-bit-correction—2-bit error detection using 8 bit ECC code in the case of 64 bit data with a small data width.
The “SEC-DED” mentioned above is an abbreviation for Single bit Error Correction-Double bit Error Detecting, and is a code for one-bit-correction—two bit error detection based on the Hamming code. Also, among SbEC-DbED (Single b-bit byte Error Correcting-Double b-bit byte Error Detecting) code based on the Reed-Solomon code, the “S4EC-D4ED” is a two type error correction code for signal byte error correction capable of correcting four bits (b=4) as one byte.
As shown in the above background art, a check code is utilized to check the memory data and an example of the art is JP Patent Publication (Kokai) No. 8-138391 A (1996).